The present disclosure relates to a semiconductor memory device, and more particularly, to a skew signal generation circuit, which extracts a current characteristic of a transistor in an impedance calibrator and generates a skew signal for controlling the timing of internal circuits, and a semiconductor memory device having the same.
Generally, a termination resistor having the same resistance as a characteristic resistance of a transmission channel is connected to a receiving terminal or a transmitting terminal of a semiconductor device. The termination resistor suppresses reflection of signals being transmitted through the transmission channel by matching the characteristic impedance of the transmission channel with the impedance of the receiving terminal or the transmitting terminal. Conventionally, the termination resistor has been installed outside a semiconductor chip. Recently, an on-die termination (ODT) is widely used. The ODT includes a termination resistor inside a semiconductor chip. The ODT includes a switching circuit that is switched on/off to control a current flowing inside. Therefore, compared with the termination resistor installed outside the chip, the ODT has low power consumption. However, the resistance of the ODT needs to be calibrated because the resistance of the ODT varies with process, voltage and temperature (PVT).
In a double data rate-3 (DDR3) memory device, an impedance (ZQ) calibration circuit is used to calibrate the resistance of an ODT. An output impedance calibration circuit includes an external resistor (ZQ) between an extra output terminal separated from a DQ terminal of the ODT and a ground terminal. The external resistor (ZQ) has a constant resistance with respect to variation of PVT. Therefore, the output impedance calibration circuit controls a pull-up drivability of a DQ terminal of the ODT according to the variation of PVT, especially skew variation of a transistor. The skew of the transistor is a parameter representing a current characteristic of the transistor and is classified into “SLOW”, “TYPICAL”, and “FAST” according to the current characteristic required by a manufacturer. The “SLOW” state represents that an amount of a current is small, the “TYPICAL” state represents that an amount of a current is normal, and the “FAST” state represents that an amount of a current is large.
The output impedance of the ODT is calibrated according to the skew variation of the transistor. However, output impedances of other internal circuits included in the semiconductor memory device are not calibrated according to the skew variation of the transistor.